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MC10H642, MC100H642 68030/040 PECL to TTL Clock Driver
Description
The MC10H/100H642 generates the necessary clocks for the 68030, 68040 and similar microprocessors. It is guaranteed to meet the clock specifications required by the 68030 and 68040 in terms of part-to-part skew, within-part skew and also duty cycle skew. The user has a choice of using either TTL or PECL (ECL referenced to +5.0 V) for the input clock. TTL clocks are typically used in present MPU systems. However, as clock speeds increase to 50 MHz and beyond, the inherent superiority of ECL (particularly differential ECL) as a means of clock signal distribution becomes increasingly evident. The H642 also uses differential PECL internally to achieve its superior skew characteristic. The H642 includes divide-by-two and divide-by-four stages, both to achieve the necessary duty cycle skew and to generate MPU clocks as required. A typical 50 MHz processor application would use an input clock running at 100 MHz, thus obtaining output clocks at 50 MHz and 25 MHz (see Logic Diagram). The 10H version is compatible with MECL 10HTM ECL logic levels, while the 100H version is compatible with 100K levels (referenced to +5.0 V).
Features
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PLCC-28 FN SUFFIX CASE 776
MARKING DIAGRAM*
1
MCxxxH642G AWLYYWW
* * * * * * *
Generates Clocks for 68030/040 Meets 030/040 Skew Requirements TTL or PECL Input Clock Extra TTL and PECL Power/Ground Pins Asynchronous Reset Single +5.0 V Supply Pb-Free Packages are Available*
xxx A WL YY WW G
= 10 or 100 = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
Function
Reset(R): LOW on RESET forces all Q outputs LOW. Select(SEL): LOW selects the ECL input source (DE/DE). HIGH selects the TTL input source (DT). The H642 also contains circuitry to force a stable input state of the ECL differential input pair, should both sides be left open. In this Case, the DE side of the input is pulled LOW, and DE goes HIGH. Power Up: The device is designed to have positive edges of the /2 and /4 outputs synchronized at Power Up.
*For additional marking information, refer to Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
November, 2006 - Rev. 8
1
Publication Order Number: MC10H642/D
MC10H642, MC100H642
VT 25 Q2 GT GT Q3 VT VT 26 27 28 1 2 3 4 5 Q5 6 GT 7 GT 8 Q6 9 Q7 10 VT 11 SEL R VT 24 Q1 23 GT 22 GT 21 Q0 20 VT 19 18 17 16 15 14 13 12 VBB DE DE VE R GE SEL DT TTL Control Inputs /2
Q2
TTL Outputs
Q7
TTL/ECL Clock Inputs VBB DE DE DT /4
Q6
Q5
MUX
Q4
Q3
Q4
Q1
Figure 1. Pinout: PLCC-28 (Top View)
Q0
Figure 2. Logic Diagram
Table 1. PIN DESCRIPTION
Pin 81 82 83 84 85 86 87 88 89 10 11 12 13 14 * Divide by 2 **Divide by 4 Symbol Q3 VT VT Q4 Q5 GT GT Q6 Q7 VT SEL DT GE R Description Signal Output (TTL)** TTL VCC (+5.0 V) TTL VCC (+5.0 V) Signal Output (TTL)** Signal Output (TTL)** TTL Ground (0 V) TTL Ground (0 V) Signal Output (TTL)** Signal Output (TTL)** TTL VCC (+5.0 V) Input Select (TTL) TTL Signal Input ECL Ground (0 V) Reset (TTL) Pin 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Symbol VE DE DE VBB VT Q0 GT GT Q1 VT VT Q2 GT GT Description ECL VCC (+5.0 V) ECL Signal Input (Non-Inverting) ECL Signal Input (Inverting) VBB Reference Output TTL VCC (+5.0 V) Signal Output (TTL)* TTL Ground (0 V) TTL Ground (0 V) Signal Output (TTL)* TTL VCC (+5.0 V) TTL VCC (+5.0 V) Signal Output (TTL)** TTL Ground (0 V) TTL Ground (0 V)
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MC10H642, MC100H642
Table 2. 10H PECL CHARACTERISTICS (VT = VE = 5.0 V 5%)
TA = 0C Symbol IINH IINL VIH VIL VBB Characteristic Input HIGH Current Input LOW Current Input HIGH Voltage (Note 1) Input LOW Voltage (Note 1) Output Reference Voltage (Note 1) VEE = 5.0 V Condition Min 0.5 3.83 3.05 3.62 Max 255 4.16 3.52 3.73 TA = 25C Min 0.5 3.87 3.05 3.65 Max 175 4.19 3.52 3.75 TA = 85C Min 0.5 3.94 3.05 3.69 Max 175 4.28 3.555 3.81 Unit mA V V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. PECL LEVELS are referenced to VCC and will vary 1:1 with the power supply. The VALUES shown are for VCC = 5.0 V.
Table 3. 100H PECL CHARACTERISTICS (VT = VE = 5.0 V 5%)
TA = 0C Symbol IINH IINL VIH VIL VBB Characteristic Input HIGH Current Input LOW Current Input HIGH Voltage (Note 2) Input LOW Voltage (Note 2) Output Reference Voltage (Note 2) VEE = 5.0 V Condition Min 0.5 3.835 3.190 3.620 Max 255 4.120 3.525 3.740 TA = 25C Min 0.5 3.835 3.190 3.620 Max 175 4.120 3.525 3.740 TA = 85C Min 0.5 3.835 3.190 3.620 Max 175 4.120 3.525 3.740 Unit mA V V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. PECL LEVELS are referenced to VCC and will vary 1:1 with the power supply. The VALUES shown are for VCC = 5.0 V.
Table 4. 10H/100H DC CHARACTERISTICS (VT = VE = 5.0 V 5%)
TA = 0C Symbol IEE ICCH ICCL Characteristic Power Supply Current PECL TTL Condition VE Pin Total All VT Pins Min Max 57 30 30 TA = 25C Min Max 57 30 30 TA = 85C Min Max 57 30 30 Unit mA mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.
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MC10H642, MC100H642
Table 5. 10H/100H TTL DC CHARACTERISTICS (VT = VE = 5.0 V 5%)
TA = 0C Symbol VIH VIL IIH IIL VOH VOL VIK IOS Characteristic Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Output HIGH Voltage Output LOW Voltage Input Clamp Voltage Output Short Circuit Current VIN = 2.7 V VIN = 7.0 V VIN = 0.5 V IOH = -3.0 mA IOH = -15 mA IOL = 24 mA IIN = -18 mA VOUT = 0 V -100 2.5 2.0 0.5 -1.2 -225 -100 Condition Min 2.0 Max 0.8 20 100 -0.6 2.5 2.0 0.5 -1.2 -225 -100 TA = 25C Min 2.0 Max 0.8 20 100 -0.6 2.5 2.0 0.5 -1.2 -225 TA = 85C Min 2.0 Max 0.8 20 100 -0.6 Unit V mA mA V V V mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.
Table 6. AC CHARACTERISTICS (VT = VE = 5.0 V 5%)
TA = 0C Symbol tPLH Characteristic Propagation Delay D to Output Part-to-Part Skew Within-Device Skew Propagation Delay D to Output Part-to-Part Skew Within-Device Skew Propagation Delay R to Output Output Rise/Fall Time 0.8 V to 2.0 V Maximum Input Frequency Reset Pulse Width Reset Recovery Time All Outputs All Outputs Q0, Q1 C ECL C TTL All Outputs CL = 25 pF 4.30 4.30 Q2-Q7 C ECL C TTL Condition CL = 25 pF Min 4.70 4.70 Max 5.70 5.70 1.0 0.5 5.30 5.30 2.0 1.0 4.3 6.3 2.5 2.5 100 1.5 1.25 100 1.5 1.25 4.0 4.50 4.50 TA = 25C Min 4.75 4.75 Max 5.75 5.75 1.0 0.5 5.50 5.50 2.0 1.0 6.0 2.5 2.5 100 1.5 1.25 4.5 4.25 4.25 TA = 85C Min 4.60 4.50 Max 5.60 5.50 1.0 0.5 5.25 5.25 2.0 1.0 6.5 2.5 2.5 Unit ns
tskpp tskwd* tPLH
ns ns ns
tskpp tskwd tPD tR tF fMAX** RPW RRT
CL = 25 pF CL = 25 pF CL = 25 pF CL = 25 pF CL = 25 pF
ns ns ns ns MHz ns ns
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. * Within-Device Skew defined as identical transactions on similar paths through a device. **MAX Frequency is 135 MHz.
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MC10H642, MC100H642
10/100H642 - DUTY CYCLE CONTROL To maintain a duty cycle of 5% at 50 MHz, limit the load capacitance and/or power supply variation as shown in Figures 1 and 2. For a 2.5% duty cycle limit, see Figures 3 and 4. Figures 5 and 6 show duty cycle variation with temperature. Figure 7 shows typical TPD versus load. Figure 8 shows reset recovery time. Figure 9 shows output states after power up. Best duty cycle control is obtained with a single mP load and minimum line length.
11 11 NEGATIVE PULSE WIDTH (ns)
POSITIVE PULSE WIDTH (ns)
10
4.75 5.00 5.25
10
4.75 5.00 5.25
9 9 0 10 20 30 40 50 60 CAPACITIVE LOAD (pF)
0
10
20 30 40 50 CAPACITIVE LOAD (pF)
60
Figure 3. MC10H642 Positive PW versus Load @ 5% VCC, TA = 25C
10.6 NEGATIVE PULSE WIDTH (ns) 10.4 10.2 10.0 9.8 9.6 9.4 9.2 0 10 20 30 40 CAPACITIVE LOAD (pF) 50 60 4.875 5.00 5.125
Figure 4. MC10H642 Negative PW versus Load @ 5% VCC, TA = 25C
10.8 10.6 10.4 10.2 10.0 9.8 9.6 9.4 0 10 CAPACITIVE LOAD (pF) 40 20 30 50 60 4.875 5.00 5.125
POSITIVE PULSE WIDTH (ns)
Figure 5. MC10H642 Positive PW versus Load @ 2.5% VCC, TA = 25C
10.4 POSITIVE PULSE WIDTH (ns) NEGATIVE PULSE WIDTH (ns) 10.2 10.0 9.8 9.6 9.4
Figure 6. MC10H642 Negative PW versus Load @ 2.5% VCC, TA = 25C
10.5 10.3 10.1 9.9 9.7 9.5 0 20 40 60 TEMPERATURE (C) 80 100 0 pF 25 pF 50 pF
0 pF 25 pF 50 pF
0
20
40 60 TEMPERATURE (C)
80
100
Figure 7. MC10H642 Positive PW versus Temperature, VCC = 5.0 V
Figure 8. MC10H642 Negative PW versus Temperature, VCC = 5.0 V
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MC10H642, MC100H642
6.2
6.0
Tpd (ns)
5.8
4.75 5.00
5.6
5.25
5.4
5.2
0
10
20
30
40
50
60
CAPACITIVE (pF)
Figure 9. MC10H642 + Tpd versus Load, VCC 5%, TA = 25C (Overshoot at 50 MHz with no load makes graph non linear)
DT
RESET, R R Q0 Q2 Q1 Q7 tpw
R trec
MC10/100H642 Figure 10. Clock Phase and Reset Recovery Time After Reset Pulse
MC10/100H642
Din
Q0.Q1
Q4 & Q5
Q2
Q7
After Power Up Figure 11. Outputs Q2 Q7 will Synchronize with Pos Edges of Din & Q0 Q1
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MC10H642, MC100H642
Switching Circuit PECL: PECL
USE 0.1 mF CAPACITORS FOR DECOUPLING. 50 W COAX PULSE GENERATOR DEVICE UNDER TEST VEE VCC & VCCO
TTL
+7 V OPEN ALL OTHERS tPZL, tPLZ R1 500 W
IN
OUT 450 W 50 COAX
USE OSCILLOSCOPE INTERNAL 50 W LOAD FOR TERMINATION.
CH A OSCILLOSCOPE
Figure 12. Switching Circuit and Waveforms
50 COAX
DEVICE UNDER TEST 50 pF
R2 500 W
CH B
PECL/TTL
PECL/TTL
50%/1.5 V Vin
80%/2.0 V Vout 20%/0.8 V
Tpd++ 50%/1.5 V
Tpd--
Trise
Tfall
Vout
Figure 14. Waveforms: Rise and Fall Times
Figure 13. Propagation Delay -- Single-Ended
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MC10H642, MC100H642
ORDERING INFORMATION
Device MC10H642FN MC10H642FNG MC10H642FNR2 MC10H642FNR2G MC100H642FN MC100H642FNG MC100H642FNR2 MC100H642FNR2G Package PLCC-28 PLCC-28 (Pb-Free) PLCC-28 PLCC-28 (Pb-Free) PLCC-28 PLCC-28 (Pb-Free) PLCC-28 PLCC-28 (Pb-Free) Shipping 37 Units / Rail 37 Units / Rail 500 / Tape & Reel 500 / Tape & Reel 37 Units / Rail 37 Units / Rail 500 / Tape & Reel 500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1672/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - ECLinPSt I/O SPiCE Modeling Kit - Metastability and the ECLinPS Family - Interfacing Between LVDS and ECL - The ECL Translator Guide - Odd Number Counters Design - Marking and Date Codes - Termination of ECL Logic Devices - Interfacing with ECLinPS - AC Characteristics of ECL Devices
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MC10H642, MC100H642
PACKAGE DIMENSIONS
PLCC-28 FN SUFFIX PLASTIC PLCC PACKAGE CASE 776-02 ISSUE E
Y BRK D Z -L- -M- B 0.007 (0.180) U
M
T L-M
M
S
N
S S
-N-
0.007 (0.180)
T L-M
N
S
W
28 1
D
V
X VIEW D-D
G1
0.010 (0.250)
S
T L-M
S
N
S
A Z R E G G1 0.010 (0.250)
S
0.007 (0.180) 0.007 (0.180)
M M
T L-M T L-M
S S
N N
S S
H
0.007 (0.180)
M
T L-M
S
N
S
C
K1 0.004 (0.100) -T- SEATING
PLANE
J
K F VIEW S 0.007 (0.180)
M
VIEW S T L-M
S
T L-M
S
N
S
N
S
NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
DIM A B C E F G H J K R U V W X Y Z G1 K1
INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --- 0.025 --- 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 --- 0.020 2_ 10_ 0.410 0.430 0.040 ---
MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 --- 0.64 --- 11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 --- 0.50 2_ 10_ 10.42 10.92 1.02 ---
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MC10H642, MC100H642
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC). MECL 10H is a trademark of Motorola, Inc.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
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MC10H642/D

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